Remove todos

verilog2logicworld/src/router.rs

@@ -214,7 +214,7 @@ pub fn route(module: Module) -> Result<(Vec<lw::Component>, Vec<lw::Wire>), Erro
         let output_address = &connection_map[&net.connected_output.unwrap_or(Connection {
             cell_index: *id,
             port_name: "input",
-            bit_index: 0, // TODO: figure out
+            bit_index: 0,
         })];
         for input in &net.connected_inputs {
             println!("input: {:?}", input);
@@ -231,7 +231,7 @@ pub fn route(module: Module) -> Result<(Vec<lw::Component>, Vec<lw::Wire>), Erro
             let input_address = &connection_map[&Connection {
                 cell_index: *id,
                 port_name: "output",
-                bit_index: 0, // TODO: figure out
+                bit_index: 0,
             }];
             wires.push(lw::Wire {
                 first_point: output_address.clone(),