From df70909542751721d5e4f7b5533c9d27244f2cee Mon Sep 17 00:00:00 2001
From: D4VID <d4vid@d4vid.xyz>
Date: Sat, 30 Aug 2025 16:51:59 +0200
Subject: [PATCH] Remove todos

---
 verilog2logicworld/src/router.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/verilog2logicworld/src/router.rs b/verilog2logicworld/src/router.rs
index 5f1f9e1..a498bf1 100644
--- a/verilog2logicworld/src/router.rs
+++ b/verilog2logicworld/src/router.rs
@@ -214,7 +214,7 @@ pub fn route(module: Module) -> Result<(Vec<lw::Component>, Vec<lw::Wire>), Erro
         let output_address = &connection_map[&net.connected_output.unwrap_or(Connection {
             cell_index: *id,
             port_name: "input",
-            bit_index: 0, // TODO: figure out
+            bit_index: 0,
         })];
         for input in &net.connected_inputs {
             println!("input: {:?}", input);
@@ -231,7 +231,7 @@ pub fn route(module: Module) -> Result<(Vec<lw::Component>, Vec<lw::Wire>), Erro
             let input_address = &connection_map[&Connection {
                 cell_index: *id,
                 port_name: "output",
-                bit_index: 0, // TODO: figure out
+                bit_index: 0,
             }];
             wires.push(lw::Wire {
                 first_point: output_address.clone(),