Remove debug map print

3 weeks ago · 86ecdca0e9
parent eca62daf30
commit 86ecdca0e9
1 changed files with 0 additions and 1 deletions
--- a/verilog2logicworld/src/router.rs
+++ b/verilog2logicworld/src/router.rs
@ -211,7 +211,6 @@ pub fn route(module: Module) -> Result<(Vec<lw::Component>, Vec<lw::Wire>), Erro
    for (id, net) in &net_list {
        println!();
        println!("{}: {:#?}", id, net);
-        println!("map; {:#?}", connection_map.keys());
        let output_address = &connection_map[&net.connected_output.unwrap_or(Connection {
            cell_index: *id,
            port_name: "input",