From 86ecdca0e92b87eaf8b1a3dd5357980cd8e70204 Mon Sep 17 00:00:00 2001
From: D4VID <d4vid@d4vid.xyz>
Date: Sat, 30 Aug 2025 16:51:17 +0200
Subject: [PATCH] Remove debug map print

---
 verilog2logicworld/src/router.rs | 1 -
 1 file changed, 1 deletion(-)

diff --git a/verilog2logicworld/src/router.rs b/verilog2logicworld/src/router.rs
index ddcdce4..5f1f9e1 100644
--- a/verilog2logicworld/src/router.rs
+++ b/verilog2logicworld/src/router.rs
@@ -211,7 +211,6 @@ pub fn route(module: Module) -> Result<(Vec<lw::Component>, Vec<lw::Wire>), Erro
     for (id, net) in &net_list {
         println!();
         println!("{}: {:#?}", id, net);
-        println!("map; {:#?}", connection_map.keys());
         let output_address = &connection_map[&net.connected_output.unwrap_or(Connection {
             cell_index: *id,
             port_name: "input",