Remove debug map print

verilog2logicworld/src/router.rs

@@ -211,7 +211,6 @@ pub fn route(module: Module) -> Result<(Vec<lw::Component>, Vec<lw::Wire>), Erro
     for (id, net) in &net_list {
         println!();
         println!("{}: {:#?}", id, net);
-        println!("map; {:#?}", connection_map.keys());
         let output_address = &connection_map[&net.connected_output.unwrap_or(Connection {
             cell_index: *id,
             port_name: "input",