Add exit codes

verilog2logicworld/src/main.rs

@@ -19,18 +19,16 @@ struct Args {
     files: Vec<String>,
 }
 
-
 fn main() {
     let args = Args::parse();
 
     let files: Vec<&str> = args.files.iter().map(|f| f.as_str()).collect();
 
     let result = get_modules(&files);
-    println!("{:?}", result);
 
     let Ok(modules) = result else {
         println!("Error while getting modules: {:?}", result);
-        return;
+        std::process::exit(1);
     };
 
     for module_name in modules {
@@ -40,7 +38,7 @@ fn main() {
             Ok(module) => module,
             Err(err) => {
                 println!("Error while compiling module {}: {:?}", module_name, err);
-                return;
+                std::process::exit(2);
             }
         };
 
@@ -49,16 +47,18 @@ fn main() {
             Ok(pair) => pair,
             Err(err) => {
                 println!("Error while routing module {}: {:?}", module_name, err);
-                return;
+                std::process::exit(3);
             }
         };
 
-        let result = create_subassembly(
+        let result = create_subassembly(module_name, &Path::new(&args.output), &components, &wires);
-            module_name,
+        match result {
-            &Path::new(&args.output),
+            Ok(_) => {}
-            &components,
+            Err(err) => {
-            &wires,
+                println!("Error while creating subassembly: {:?}", err);
-        );
+                std::process::exit(4);
-        println!("{:?}", result);
+            }
+        };
+        println!("Success");
     }
 }