From 501881def1582c2e583886a5f340f69b5ba7a0c0 Mon Sep 17 00:00:00 2001
From: D4VID <d4vid@d4vid.xyz>
Date: Wed, 20 Aug 2025 20:05:46 +0200
Subject: [PATCH] Add exit codes

---
 verilog2logicworld/src/main.rs | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/verilog2logicworld/src/main.rs b/verilog2logicworld/src/main.rs
index ed7c79b..5b4aba3 100644
--- a/verilog2logicworld/src/main.rs
+++ b/verilog2logicworld/src/main.rs
@@ -19,18 +19,16 @@ struct Args {
     files: Vec<String>,
 }
 
-
 fn main() {
     let args = Args::parse();
 
     let files: Vec<&str> = args.files.iter().map(|f| f.as_str()).collect();
 
     let result = get_modules(&files);
-    println!("{:?}", result);
 
     let Ok(modules) = result else {
         println!("Error while getting modules: {:?}", result);
-        return;
+        std::process::exit(1);
     };
 
     for module_name in modules {
@@ -40,7 +38,7 @@ fn main() {
             Ok(module) => module,
             Err(err) => {
                 println!("Error while compiling module {}: {:?}", module_name, err);
-                return;
+                std::process::exit(2);
             }
         };
 
@@ -49,16 +47,18 @@ fn main() {
             Ok(pair) => pair,
             Err(err) => {
                 println!("Error while routing module {}: {:?}", module_name, err);
-                return;
+                std::process::exit(3);
             }
         };
 
-        let result = create_subassembly(
-            module_name,
-            &Path::new(&args.output),
-            &components,
-            &wires,
-        );
-        println!("{:?}", result);
+        let result = create_subassembly(module_name, &Path::new(&args.output), &components, &wires);
+        match result {
+            Ok(_) => {}
+            Err(err) => {
+                println!("Error while creating subassembly: {:?}", err);
+                std::process::exit(4);
+            }
+        };
+        println!("Success");
     }
 }