Improve inputs and outputs

(Straight throught other components)

verilog2logicworld/src/main.rs

@@ -39,7 +39,7 @@ fn main() {
 
         let result = create_subassembly(
             module_name,
-            &Path::new("/mnt/SSD_DATA/Steam/steamapps/common/Logic World/subassemblies"),
+            &Path::new("output/"),
             &components,
             &wires,
         );