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5faead9fc6
...
eca62daf30
@ -1,185 +0,0 @@
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use std::cmp::max;
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use logicworld_subassembly::{lw, COMPONENT_MAP};
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use vecmath::{vec3_add, Vector3};
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use crate::cells::builder;
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use crate::router::{Connection, ConnectionMap, SQUARE};
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use crate::verilog::Cell;
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pub fn binary_op(
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cell: &Cell,
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text_id: &str,
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parent_address: u32,
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next_address: &mut u32,
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next_position: &mut Vector3<i32>,
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wires: &mut Vec<lw::Wire>,
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connection_map: &mut ConnectionMap,
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) -> Vec<lw::Component> {
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// All binary RTL cells have two input ports \A and \B and one output port \Y. They also have the following parameters:
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// Set to a non-zero value if the input \A is signed and therefore should be sign-extended when needed.
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let a_signed = cell.parameters["A_SIGNED"] > 0;
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// The width of the input port \A.
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let a_width = cell.parameters["A_WIDTH"];
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// Set to a non-zero value if the input \B is signed and therefore should be sign-extended when needed.
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let b_signed = cell.parameters["B_SIGNED"] > 0;
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// The width of the input port \B.
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let b_width = cell.parameters["B_WIDTH"];
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// The width of the output port \Y.
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let y_width = cell.parameters["Y_WIDTH"];
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assert!(a_width == b_width, "Different widths not yet supported");
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assert!(!a_signed && !b_signed, "Signed not yet supported");
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assert!(
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a_width == y_width,
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"Different widths of input and output not yet supported"
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);
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let mut components = vec![];
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let height = max(max(a_width, b_width), y_width);
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builder(
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height,
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parent_address,
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next_address,
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next_position,
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&mut components,
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wires,
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connection_map,
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|i_bit, next_address, parent, next_position_within, components, wires, connection_map| {
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let input_a = lw::Input::new(cell.inputs["A"][i_bit] as i32);
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let input_b = lw::Input::new(cell.inputs["B"][i_bit] as i32);
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let output_state_id = cell.outputs["Y"][i_bit] as lw::Int;
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let output = lw::Output::new(output_state_id);
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if text_id == "Custom.OrGate" {
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let input_a = lw::Input::new(cell.inputs["A"][0] as lw::Int);
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let input_b = lw::Input::new(cell.inputs["B"][0] as lw::Int);
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let output_a = lw::Output::new(output_state_id);
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let output_b = lw::Output::new(output_state_id);
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let peg = lw::Input::new(output_state_id);
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let buffer_a = lw::Component {
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address: *next_address,
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parent,
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numeric_id: COMPONENT_MAP["MHG.Buffer_WithOutput"],
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position: *next_position_within,
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rotation: quaternion::id(),
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inputs: vec![input_a],
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outputs: vec![output_a],
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custom_data: vec![],
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};
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let buffer_b = lw::Component {
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address: *next_address + 1,
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parent,
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numeric_id: COMPONENT_MAP["MHG.Buffer_WithOutput"],
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position: vec3_add(*next_position_within, [SQUARE, 0, 0]),
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rotation: quaternion::id(),
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inputs: vec![input_b],
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outputs: vec![output_b],
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custom_data: vec![],
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};
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let peg = lw::Component {
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address: *next_address + 2,
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parent,
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numeric_id: COMPONENT_MAP["MHG.Peg"],
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position: vec3_add(*next_position_within, [0, 0, 2 * SQUARE]),
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rotation: quaternion::id(),
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inputs: vec![peg],
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outputs: vec![],
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custom_data: vec![],
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};
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*next_address += 3;
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connection_map.insert(
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Connection {
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cell_index: cell.index,
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port_name: "A",
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bit_index: i_bit,
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},
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lw::PegAddress::input(buffer_a.address, 0),
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);
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connection_map.insert(
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Connection {
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cell_index: cell.index,
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port_name: "B",
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bit_index: i_bit,
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},
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lw::PegAddress::input(buffer_b.address, 0),
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);
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connection_map.insert(
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Connection {
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cell_index: cell.index,
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port_name: "Y",
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bit_index: i_bit,
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},
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lw::PegAddress::input(peg.address, 0),
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);
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wires.push(lw::Wire {
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first_point: lw::PegAddress::output(buffer_a.address, 0),
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second_point: lw::PegAddress::input(peg.address, 0),
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circuit_state_id: output_state_id,
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wire_rotation: 0.0,
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});
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wires.push(lw::Wire {
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first_point: lw::PegAddress::output(buffer_b.address, 0),
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second_point: lw::PegAddress::input(peg.address, 0),
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circuit_state_id: output_state_id,
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wire_rotation: 0.0,
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});
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components.push(buffer_a);
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components.push(buffer_b);
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components.push(peg);
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} else {
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let component = lw::Component {
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address: *next_address,
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parent,
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numeric_id: COMPONENT_MAP[text_id],
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position: *next_position_within,
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rotation: quaternion::id(),
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inputs: vec![input_a, input_b],
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outputs: vec![output],
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custom_data: vec![],
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};
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*next_address += 1;
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connection_map.insert(
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Connection {
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cell_index: cell.index,
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port_name: "A",
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bit_index: i_bit,
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},
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lw::PegAddress::input(component.address, 0),
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);
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connection_map.insert(
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Connection {
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cell_index: cell.index,
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port_name: "B",
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bit_index: i_bit,
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},
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lw::PegAddress::input(component.address, 1),
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);
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connection_map.insert(
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Connection {
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cell_index: cell.index,
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port_name: "Y",
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bit_index: i_bit,
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},
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lw::PegAddress::output(component.address, 0),
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);
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components.push(component);
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}
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},
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);
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next_position[2] += 4 * SQUARE;
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return components;
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}
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@ -1,90 +0,0 @@
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use logicworld_subassembly::{lw, COMPONENT_MAP};
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use vecmath::Vector3;
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use crate::router::{ConnectionMap, SQUARE};
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pub fn builder(
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height: usize,
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parent_address: u32,
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next_address: &mut u32,
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position: &Vector3<i32>,
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components: &mut Vec<lw::Component>,
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wires: &mut Vec<lw::Wire>,
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connection_map: &mut ConnectionMap,
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layer_builder: impl Fn(
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usize,
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&mut u32,
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u32,
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&mut Vector3<i32>,
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&mut Vec<lw::Component>,
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&mut Vec<lw::Wire>,
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&mut ConnectionMap,
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),
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) {
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let mount = lw::Component {
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address: *next_address,
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parent: parent_address,
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numeric_id: COMPONENT_MAP["MHG.Mount"],
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position: *position,
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rotation: quaternion::id(),
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inputs: vec![],
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outputs: vec![],
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custom_data: lw::Mount::new(8).custom_data(),
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};
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let next_board = lw::Component {
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address: *next_address + 1,
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parent: mount.address,
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numeric_id: COMPONENT_MAP["MHG.CircuitBoard"],
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position: [-SQUARE / 2, 3 * SQUARE - SQUARE / 3, -SQUARE / 2],
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rotation: quaternion::id(),
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inputs: vec![],
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outputs: vec![],
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custom_data: lw::CircuitBoard::default().with_size(3, 2).custom_data(),
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};
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*next_address += 2;
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let mut next_parent = next_board.address;
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components.push(mount);
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components.push(next_board);
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for i_bit in 0..height {
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let mut next_position_within = [SQUARE / 2, SQUARE / 2, SQUARE / 2];
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let mount = lw::Component {
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address: *next_address,
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parent: next_parent,
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numeric_id: COMPONENT_MAP["MHG.Mount"],
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position: next_position_within,
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rotation: quaternion::id(),
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inputs: vec![],
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outputs: vec![],
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custom_data: lw::Mount::new(8).custom_data(),
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};
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let next_board = lw::Component {
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address: *next_address + 1,
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parent: mount.address,
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numeric_id: COMPONENT_MAP["MHG.CircuitBoard"],
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position: [-SQUARE / 2, 3 * SQUARE - SQUARE / 3, -SQUARE / 2],
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rotation: quaternion::id(),
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inputs: vec![],
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outputs: vec![],
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custom_data: lw::CircuitBoard::default().with_size(3, 2).custom_data(),
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};
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*next_address += 2;
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next_position_within[0] += SQUARE;
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layer_builder(
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i_bit,
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next_address,
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next_parent,
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&mut next_position_within,
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components,
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wires,
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connection_map,
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);
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next_parent = next_board.address;
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components.push(mount);
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components.push(next_board);
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}
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}
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@ -1,73 +0,0 @@
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use std::f32::consts::PI;
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use logicworld_subassembly::{lw, COMPONENT_MAP};
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use vecmath::{vec3_add, Vector3};
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use crate::cells::builder;
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use crate::router::{Connection, ConnectionMap, SQUARE};
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pub fn input_port(
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bits: &Vec<usize>,
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port_name: &str,
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parent_address: u32,
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next_address: &mut u32,
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next_position: &mut Vector3<lw::Int>,
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connection_map: &mut ConnectionMap,
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) -> Vec<lw::Component> {
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let mut components = vec![];
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let mut wires = vec![]; // discard
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builder(
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bits.len(),
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parent_address,
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next_address,
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next_position,
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&mut components,
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&mut wires,
|
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connection_map,
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|i_bit, next_address, parent, next_position_within, components, _wires, connection_map| {
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let bit_id = bits[i_bit];
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let label = lw::Component {
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address: *next_address,
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parent,
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numeric_id: COMPONENT_MAP["MHG.PanelLabel"],
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position: *next_position_within,
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rotation: quaternion::euler_angles(0.0, -PI / 2.0, 0.0),
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inputs: vec![],
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outputs: vec![],
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custom_data: lw::Label::new(&format!("{}[{}]", port_name, i_bit))
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.with_size(2.0)
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.custom_data(),
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};
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*next_address += 1;
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let peg = lw::Component {
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address: *next_address,
|
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parent,
|
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numeric_id: COMPONENT_MAP["MHG.Peg"],
|
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position: vec3_add(*next_position_within, [0, 0, SQUARE]),
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rotation: quaternion::id(),
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inputs: vec![lw::Input::new(bit_id as lw::Int)],
|
|
||||||
outputs: vec![],
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||||||
custom_data: vec![],
|
|
||||||
};
|
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||||||
connection_map.insert(
|
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||||||
Connection {
|
|
||||||
cell_index: bit_id,
|
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||||||
port_name: "input",
|
|
||||||
bit_index: 0,
|
|
||||||
},
|
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||||||
lw::PegAddress::input(peg.address, 0),
|
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||||||
);
|
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||||||
|
|
||||||
components.push(label);
|
|
||||||
components.push(peg);
|
|
||||||
|
|
||||||
*next_address += 1;
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||||||
},
|
|
||||||
);
|
|
||||||
|
|
||||||
next_position[0] += SQUARE / 3; // third of a square
|
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||||||
|
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||||||
return components;
|
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||||||
}
|
|
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@ -1,12 +0,0 @@
|
|||||||
mod builder;
|
|
||||||
use builder::builder;
|
|
||||||
|
|
||||||
pub mod unary_op;
|
|
||||||
pub mod binary_op;
|
|
||||||
pub mod input_port;
|
|
||||||
pub mod output_port;
|
|
||||||
|
|
||||||
pub use unary_op::unary_op;
|
|
||||||
pub use binary_op::binary_op;
|
|
||||||
pub use output_port::output_port;
|
|
||||||
pub use input_port::input_port;
|
|
||||||
@ -1,73 +0,0 @@
|
|||||||
use std::f32::consts::PI;
|
|
||||||
|
|
||||||
use logicworld_subassembly::{lw, COMPONENT_MAP};
|
|
||||||
use vecmath::{vec3_add, Vector3};
|
|
||||||
|
|
||||||
use crate::cells::builder;
|
|
||||||
use crate::router::{Connection, ConnectionMap, SQUARE};
|
|
||||||
|
|
||||||
pub fn output_port(
|
|
||||||
bits: &Vec<usize>,
|
|
||||||
port_name: &str,
|
|
||||||
parent_address: u32,
|
|
||||||
next_address: &mut u32,
|
|
||||||
next_position: &mut Vector3<lw::Int>,
|
|
||||||
connection_map: &mut ConnectionMap,
|
|
||||||
) -> Vec<lw::Component> {
|
|
||||||
let mut components = vec![];
|
|
||||||
let mut wires = vec![]; // discard
|
|
||||||
builder(
|
|
||||||
bits.len(),
|
|
||||||
parent_address,
|
|
||||||
next_address,
|
|
||||||
next_position,
|
|
||||||
&mut components,
|
|
||||||
&mut wires,
|
|
||||||
connection_map,
|
|
||||||
|i_bit, next_address, parent, next_position_within, components, _wires, connection_map| {
|
|
||||||
let bit_id = bits[i_bit];
|
|
||||||
let label = lw::Component {
|
|
||||||
address: *next_address,
|
|
||||||
parent,
|
|
||||||
numeric_id: COMPONENT_MAP["MHG.PanelLabel"],
|
|
||||||
position: vec3_add(*next_position_within, [0, 0, SQUARE]),
|
|
||||||
rotation: quaternion::euler_angles(0.0, -PI / 2.0, 0.0),
|
|
||||||
inputs: vec![],
|
|
||||||
outputs: vec![],
|
|
||||||
custom_data: lw::Label::new(&format!("{}[{}]", port_name, i_bit))
|
|
||||||
.with_size(2.0)
|
|
||||||
.custom_data(),
|
|
||||||
};
|
|
||||||
|
|
||||||
*next_address += 1;
|
|
||||||
|
|
||||||
let peg = lw::Component {
|
|
||||||
address: *next_address,
|
|
||||||
parent,
|
|
||||||
numeric_id: COMPONENT_MAP["MHG.Peg"],
|
|
||||||
position: *next_position_within,
|
|
||||||
rotation: quaternion::id(),
|
|
||||||
inputs: vec![lw::Input::new(bit_id as lw::Int)],
|
|
||||||
outputs: vec![],
|
|
||||||
custom_data: vec![],
|
|
||||||
};
|
|
||||||
|
|
||||||
connection_map.insert(
|
|
||||||
Connection {
|
|
||||||
cell_index: bit_id,
|
|
||||||
port_name: "output",
|
|
||||||
bit_index: 0,
|
|
||||||
},
|
|
||||||
lw::PegAddress::input(peg.address, 0),
|
|
||||||
);
|
|
||||||
|
|
||||||
components.push(label);
|
|
||||||
components.push(peg);
|
|
||||||
|
|
||||||
*next_address += 1;
|
|
||||||
},
|
|
||||||
);
|
|
||||||
next_position[0] += SQUARE / 3; // third of a square
|
|
||||||
|
|
||||||
return components;
|
|
||||||
}
|
|
||||||
@ -1,86 +0,0 @@
|
|||||||
use std::cmp::max;
|
|
||||||
|
|
||||||
use logicworld_subassembly::{lw, COMPONENT_MAP};
|
|
||||||
use vecmath::Vector3;
|
|
||||||
|
|
||||||
use crate::cells::builder;
|
|
||||||
use crate::router::{Connection, ConnectionMap, SQUARE};
|
|
||||||
use crate::verilog::Cell;
|
|
||||||
|
|
||||||
pub fn unary_op(
|
|
||||||
cell: &Cell,
|
|
||||||
text_id: &str,
|
|
||||||
parent_address: u32,
|
|
||||||
next_address: &mut u32,
|
|
||||||
next_position: &mut Vector3<i32>,
|
|
||||||
wires: &mut Vec<lw::Wire>,
|
|
||||||
connection_map: &mut ConnectionMap,
|
|
||||||
) -> Vec<lw::Component> {
|
|
||||||
// All unary RTL cells have one input port \A and one output port \Y. They also have the following parameters:
|
|
||||||
|
|
||||||
// Set to a non-zero value if the input \A is signed and therefore should be sign-extended when needed.
|
|
||||||
let a_signed = cell.parameters["A_SIGNED"] > 0;
|
|
||||||
|
|
||||||
// The width of the input port \A.
|
|
||||||
let a_width = cell.parameters["A_WIDTH"];
|
|
||||||
|
|
||||||
// The width of the output port \Y.
|
|
||||||
let y_width = cell.parameters["Y_WIDTH"];
|
|
||||||
|
|
||||||
assert!(!a_signed, "Signed not yet supported");
|
|
||||||
assert!(
|
|
||||||
a_width == y_width,
|
|
||||||
"Different widths of input and output not yet supported"
|
|
||||||
);
|
|
||||||
|
|
||||||
let mut components = vec![];
|
|
||||||
|
|
||||||
let height = max(a_width, y_width);
|
|
||||||
|
|
||||||
builder(
|
|
||||||
height,
|
|
||||||
parent_address,
|
|
||||||
next_address,
|
|
||||||
next_position,
|
|
||||||
&mut components,
|
|
||||||
wires,
|
|
||||||
connection_map,
|
|
||||||
|i_bit, next_address, parent, next_position_within, components, _wires, connection_map| {
|
|
||||||
let input = lw::Input::new(cell.inputs["A"][i_bit] as i32);
|
|
||||||
let output = lw::Output::new(cell.outputs["Y"][i_bit] as i32);
|
|
||||||
let component = lw::Component {
|
|
||||||
address: *next_address,
|
|
||||||
parent,
|
|
||||||
numeric_id: COMPONENT_MAP[text_id],
|
|
||||||
position: *next_position_within,
|
|
||||||
rotation: quaternion::id(),
|
|
||||||
inputs: vec![input],
|
|
||||||
outputs: vec![output],
|
|
||||||
custom_data: vec![],
|
|
||||||
};
|
|
||||||
|
|
||||||
connection_map.insert(
|
|
||||||
Connection {
|
|
||||||
cell_index: cell.index,
|
|
||||||
port_name: "A",
|
|
||||||
bit_index: i_bit,
|
|
||||||
},
|
|
||||||
lw::PegAddress::input(component.address, 0),
|
|
||||||
);
|
|
||||||
connection_map.insert(
|
|
||||||
Connection {
|
|
||||||
cell_index: cell.index,
|
|
||||||
port_name: "Y",
|
|
||||||
bit_index: i_bit,
|
|
||||||
},
|
|
||||||
lw::PegAddress::output(component.address, 0),
|
|
||||||
);
|
|
||||||
|
|
||||||
components.push(component);
|
|
||||||
*next_address += 1;
|
|
||||||
},
|
|
||||||
);
|
|
||||||
next_position[2] += 3 * SQUARE;
|
|
||||||
|
|
||||||
return components;
|
|
||||||
}
|
|
||||||
Loading…
Reference in new issue