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@ -1,21 +1,41 @@
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use std::{collections::HashMap, f32::consts::PI};
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use std::{collections::HashMap, f32::consts::PI, fmt::Debug};
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use logicworld_subassembly::{lw, COMPONENT_MAP};
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use logicworld_subassembly::{lw, COMPONENT_MAP};
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use vecmath::{vec3_add, Vector3};
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use vecmath::{vec3_add, Vector3};
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use crate::verilog::{Cell, Error, Module};
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use crate::verilog::{Cell, Error, Module};
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// https://yosyshq.readthedocs.io/projects/yosys/en/0.39/CHAPTER_CellLib.html
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const SQUARE: lw::Int = 300;
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const SQUARE: lw::Int = 300;
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#[derive(Clone, Copy, PartialEq, Eq, Hash)]
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struct Connection<'a> {
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cell_index: usize,
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port_name: &'a str,
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bit_index: usize,
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}
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impl<'a> Debug for Connection<'a> {
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fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
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write!(
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f,
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"{}-{}-{}",
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self.cell_index, self.port_name, self.bit_index
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)
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}
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}
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#[derive(Default, Debug)]
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#[derive(Default, Debug)]
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struct Net<'a> {
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struct Net<'a> {
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/// Index of cell that is outputting into this net (or None, if it's the module input)
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/// Index of cell that is outputting into this net (or None, if it's the module input)
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connected_output: Option<(usize, &'a str)>,
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connected_output: Option<Connection<'a>>,
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/// Indicies and names of ports of cells whose inputs are connected to this net
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/// Indicies and names of ports of cells whose inputs are connected to this net
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connected_inputs: Vec<(usize, &'a str)>,
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connected_inputs: Vec<Connection<'a>>,
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}
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}
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type ConnectionMap<'a> = HashMap<Connection<'a>, lw::PegAddress>;
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pub fn route(module: Module) -> Result<(Vec<lw::Component>, Vec<lw::Wire>), Error> {
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pub fn route(module: Module) -> Result<(Vec<lw::Component>, Vec<lw::Wire>), Error> {
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let mut net_list: HashMap<usize, Net> = HashMap::new();
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let mut net_list: HashMap<usize, Net> = HashMap::new();
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@ -37,22 +57,30 @@ pub fn route(module: Module) -> Result<(Vec<lw::Component>, Vec<lw::Wire>), Erro
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);
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);
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}
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}
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}
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}
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for (i, cell) in module.cells.iter().enumerate() {
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for (i_cell, cell) in module.cells.iter().enumerate() {
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for (key, bits) in &cell.inputs {
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for (key, bits) in &cell.inputs {
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for bit in bits {
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for (i_bit, bit) in bits.iter().enumerate() {
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net_list
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net_list
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.entry(*bit)
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.entry(*bit)
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.or_insert(Net::default())
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.or_insert(Net::default())
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.connected_inputs
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.connected_inputs
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.push((i, key));
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.push(Connection {
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cell_index: i_cell,
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port_name: key,
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bit_index: i_bit,
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});
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}
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}
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}
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}
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for (key, bits) in &cell.outputs {
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for (key, bits) in &cell.outputs {
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for bit in bits {
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for (i_bit, bit) in bits.iter().enumerate() {
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net_list
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net_list
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.entry(*bit)
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.entry(*bit)
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.or_insert(Net::default())
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.or_insert(Net::default())
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.connected_output = Some((i, key));
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.connected_output = Some(Connection {
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cell_index: i_cell,
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port_name: key,
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bit_index: i_bit,
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});
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}
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}
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}
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}
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}
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}
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@ -69,7 +97,7 @@ pub fn route(module: Module) -> Result<(Vec<lw::Component>, Vec<lw::Wire>), Erro
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let mut input_ports: Vec<lw::Component> = vec![];
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let mut input_ports: Vec<lw::Component> = vec![];
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let mut output_ports: Vec<lw::Component> = vec![];
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let mut output_ports: Vec<lw::Component> = vec![];
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let mut connection_map: HashMap<(usize, &str), lw::PegAddress> = HashMap::new();
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let mut connection_map: ConnectionMap = HashMap::new();
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// the size of squares is 300 units
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// the size of squares is 300 units
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// 150, 150, 150 is the middle of the first square
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// 150, 150, 150 is the middle of the first square
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@ -105,6 +133,7 @@ pub fn route(module: Module) -> Result<(Vec<lw::Component>, Vec<lw::Wire>), Erro
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board_address,
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board_address,
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&mut next_address,
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&mut next_address,
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&mut next_position,
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&mut next_position,
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&mut wires,
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&mut connection_map,
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&mut connection_map,
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),
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),
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"$xor" => binary_op(
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"$xor" => binary_op(
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@ -113,10 +142,12 @@ pub fn route(module: Module) -> Result<(Vec<lw::Component>, Vec<lw::Wire>), Erro
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board_address,
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board_address,
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&mut next_address,
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&mut next_address,
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&mut next_position,
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&mut next_position,
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&mut wires,
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&mut connection_map,
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&mut connection_map,
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),
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),
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"$or" => or_gate(
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"$or" => binary_op(
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cell,
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cell,
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"Custom.OrGate",
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board_address,
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board_address,
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&mut next_address,
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&mut next_address,
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&mut next_position,
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&mut next_position,
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@ -129,6 +160,7 @@ pub fn route(module: Module) -> Result<(Vec<lw::Component>, Vec<lw::Wire>), Erro
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board_address,
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board_address,
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&mut next_address,
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&mut next_address,
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&mut next_position,
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&mut next_position,
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&mut wires,
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&mut connection_map,
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&mut connection_map,
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),
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),
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_ => return Err(Error::UnsupportedCell),
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_ => return Err(Error::UnsupportedCell),
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@ -178,10 +210,15 @@ pub fn route(module: Module) -> Result<(Vec<lw::Component>, Vec<lw::Wire>), Erro
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for (id, net) in &net_list {
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for (id, net) in &net_list {
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println!();
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println!();
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println!("{}: {:?}", id, net);
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println!("{}: {:#?}", id, net);
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println!("map; {:?}", connection_map.keys());
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println!("map; {:#?}", connection_map.keys());
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let output_address = &connection_map[&net.connected_output.unwrap_or((*id, "input"))];
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let output_address = &connection_map[&net.connected_output.unwrap_or(Connection {
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cell_index: *id,
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port_name: "input",
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bit_index: 0, // TODO: figure out
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})];
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for input in &net.connected_inputs {
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for input in &net.connected_inputs {
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println!("input: {:?}", input);
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let input_address = &connection_map[input];
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let input_address = &connection_map[input];
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wires.push(lw::Wire {
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wires.push(lw::Wire {
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first_point: output_address.clone(),
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first_point: output_address.clone(),
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@ -192,7 +229,11 @@ pub fn route(module: Module) -> Result<(Vec<lw::Component>, Vec<lw::Wire>), Erro
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}
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}
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if net.connected_inputs.is_empty() {
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if net.connected_inputs.is_empty() {
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let input_address = &connection_map[&(*id, "output")];
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let input_address = &connection_map[&Connection {
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cell_index: *id,
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port_name: "output",
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bit_index: 0, // TODO: figure out
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}];
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wires.push(lw::Wire {
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wires.push(lw::Wire {
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first_point: output_address.clone(),
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first_point: output_address.clone(),
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second_point: input_address.clone(),
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second_point: input_address.clone(),
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@ -211,9 +252,8 @@ fn input_port(
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parent_address: u32,
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parent_address: u32,
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next_address: &mut u32,
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next_address: &mut u32,
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next_position: &mut Vector3<lw::Int>,
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next_position: &mut Vector3<lw::Int>,
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connection_map: &mut HashMap<(usize, &str), lw::PegAddress>,
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connection_map: &mut ConnectionMap,
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) -> Vec<lw::Component> {
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) -> Vec<lw::Component> {
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let label = lw::Component {
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let label = lw::Component {
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address: *next_address,
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address: *next_address,
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parent: parent_address,
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parent: parent_address,
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@ -237,7 +277,14 @@ fn input_port(
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outputs: vec![],
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outputs: vec![],
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custom_data: vec![],
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custom_data: vec![],
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};
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};
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connection_map.insert((bit_id, "input"), lw::PegAddress::input(peg.address, 0));
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connection_map.insert(
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Connection {
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cell_index: bit_id,
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port_name: "input",
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bit_index: 0,
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},
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lw::PegAddress::input(peg.address, 0),
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);
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*next_address += 1;
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*next_address += 1;
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next_position[0] += SQUARE / 3; // third of a square
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next_position[0] += SQUARE / 3; // third of a square
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@ -251,9 +298,8 @@ fn output_port(
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parent_address: u32,
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parent_address: u32,
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next_address: &mut u32,
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next_address: &mut u32,
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next_position: &mut Vector3<lw::Int>,
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next_position: &mut Vector3<lw::Int>,
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connection_map: &mut HashMap<(usize, &str), lw::PegAddress>,
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connection_map: &mut ConnectionMap,
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) -> Vec<lw::Component> {
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) -> Vec<lw::Component> {
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let label = lw::Component {
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let label = lw::Component {
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address: *next_address,
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address: *next_address,
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parent: parent_address,
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parent: parent_address,
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@ -277,7 +323,14 @@ fn output_port(
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outputs: vec![],
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outputs: vec![],
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custom_data: vec![],
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custom_data: vec![],
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};
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};
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connection_map.insert((bit_id, "output"), lw::PegAddress::input(peg.address, 0));
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connection_map.insert(
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Connection {
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cell_index: bit_id,
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port_name: "output",
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bit_index: 0,
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},
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lw::PegAddress::input(peg.address, 0),
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);
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*next_address += 1;
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*next_address += 1;
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next_position[0] += SQUARE / 3; // third of a square
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next_position[0] += SQUARE / 3; // third of a square
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@ -291,97 +344,49 @@ fn binary_op(
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parent_address: u32,
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parent_address: u32,
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next_address: &mut u32,
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next_address: &mut u32,
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next_position: &mut Vector3<i32>,
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next_position: &mut Vector3<i32>,
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connection_map: &mut HashMap<(usize, &str), lw::PegAddress>,
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wires: &mut Vec<lw::Wire>,
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connection_map: &mut ConnectionMap,
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) -> Vec<lw::Component> {
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) -> Vec<lw::Component> {
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let input_a = lw::Input::new(cell.inputs["A"][0] as i32);
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// All binary RTL cells have two input ports \A and \B and one output port \Y. They also have the following parameters:
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let input_b = lw::Input::new(cell.inputs["B"][0] as i32);
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let output = lw::Output::new(cell.outputs["Y"][0] as i32);
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let component = lw::Component {
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address: *next_address,
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parent: parent_address,
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numeric_id: COMPONENT_MAP[text_id],
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|
|
|
|
|
position: *next_position,
|
|
|
|
|
|
|
|
rotation: quaternion::id(),
|
|
|
|
|
|
|
|
inputs: vec![input_a, input_b],
|
|
|
|
|
|
|
|
outputs: vec![output],
|
|
|
|
|
|
|
|
custom_data: vec![],
|
|
|
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
connection_map.insert(
|
|
|
|
// Set to a non-zero value if the input \A is signed and therefore should be sign-extended when needed.
|
|
|
|
(cell.index, "A"),
|
|
|
|
let a_signed = cell.parameters["A_SIGNED"] > 0;
|
|
|
|
lw::PegAddress::input(component.address, 0),
|
|
|
|
|
|
|
|
);
|
|
|
|
|
|
|
|
connection_map.insert(
|
|
|
|
|
|
|
|
(cell.index, "B"),
|
|
|
|
|
|
|
|
lw::PegAddress::input(component.address, 1),
|
|
|
|
|
|
|
|
);
|
|
|
|
|
|
|
|
connection_map.insert(
|
|
|
|
|
|
|
|
(cell.index, "Y"),
|
|
|
|
|
|
|
|
lw::PegAddress::output(component.address, 0),
|
|
|
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
*next_address += 1;
|
|
|
|
// The width of the input port \A.
|
|
|
|
next_position[2] += 3 * SQUARE;
|
|
|
|
let a_width = cell.parameters["A_WIDTH"];
|
|
|
|
|
|
|
|
|
|
|
|
return vec![component];
|
|
|
|
// Set to a non-zero value if the input \B is signed and therefore should be sign-extended when needed.
|
|
|
|
}
|
|
|
|
let b_signed = cell.parameters["B_SIGNED"] > 0;
|
|
|
|
|
|
|
|
|
|
|
|
fn unary_op(
|
|
|
|
// The width of the input port \B.
|
|
|
|
cell: &Cell,
|
|
|
|
let b_width = cell.parameters["B_WIDTH"];
|
|
|
|
text_id: &str,
|
|
|
|
|
|
|
|
parent_address: u32,
|
|
|
|
|
|
|
|
next_address: &mut u32,
|
|
|
|
|
|
|
|
next_position: &mut Vector3<i32>,
|
|
|
|
|
|
|
|
connection_map: &mut HashMap<(usize, &str), lw::PegAddress>,
|
|
|
|
|
|
|
|
) -> Vec<lw::Component> {
|
|
|
|
|
|
|
|
let input = lw::Input::new(cell.inputs["A"][0] as i32);
|
|
|
|
|
|
|
|
let output = lw::Output::new(cell.outputs["Y"][0] as i32);
|
|
|
|
|
|
|
|
let component = lw::Component {
|
|
|
|
|
|
|
|
address: *next_address,
|
|
|
|
|
|
|
|
parent: parent_address,
|
|
|
|
|
|
|
|
numeric_id: COMPONENT_MAP[text_id],
|
|
|
|
|
|
|
|
position: *next_position,
|
|
|
|
|
|
|
|
rotation: quaternion::id(),
|
|
|
|
|
|
|
|
inputs: vec![input],
|
|
|
|
|
|
|
|
outputs: vec![output],
|
|
|
|
|
|
|
|
custom_data: vec![],
|
|
|
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
connection_map.insert(
|
|
|
|
// The width of the output port \Y.
|
|
|
|
(cell.index, "A"),
|
|
|
|
let _y_width = cell.parameters["Y_WIDTH"];
|
|
|
|
lw::PegAddress::input(component.address, 0),
|
|
|
|
|
|
|
|
);
|
|
|
|
|
|
|
|
connection_map.insert(
|
|
|
|
|
|
|
|
(cell.index, "Y"),
|
|
|
|
|
|
|
|
lw::PegAddress::output(component.address, 0),
|
|
|
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
*next_address += 1;
|
|
|
|
assert!(a_width == b_width, "Different widths not yet supported");
|
|
|
|
next_position[2] += 3 * SQUARE;
|
|
|
|
assert!(!a_signed && !b_signed, "Signed not yet supported");
|
|
|
|
|
|
|
|
|
|
|
|
return vec![component];
|
|
|
|
// let mut next_parent = parent_address;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fn or_gate(
|
|
|
|
let mut components = vec![];
|
|
|
|
cell: &Cell,
|
|
|
|
|
|
|
|
parent_address: u32,
|
|
|
|
for i_bit in 0..a_width {
|
|
|
|
next_address: &mut u32,
|
|
|
|
let input_a = lw::Input::new(cell.inputs["A"][i_bit] as i32);
|
|
|
|
next_position: &mut Vector3<lw::Int>,
|
|
|
|
let input_b = lw::Input::new(cell.inputs["B"][i_bit] as i32);
|
|
|
|
wires: &mut Vec<lw::Wire>,
|
|
|
|
let output_state_id = cell.outputs["Y"][i_bit] as lw::Int;
|
|
|
|
connection_map: &mut HashMap<(usize, &str), lw::PegAddress>,
|
|
|
|
let output = lw::Output::new(output_state_id);
|
|
|
|
) -> Vec<lw::Component> {
|
|
|
|
if text_id == "Custom.OrGate" {
|
|
|
|
let input_a = lw::Input::new(cell.inputs["A"][0] as lw::Int);
|
|
|
|
let input_a = lw::Input::new(cell.inputs["A"][0] as lw::Int);
|
|
|
|
let input_b = lw::Input::new(cell.inputs["B"][0] as lw::Int);
|
|
|
|
let input_b = lw::Input::new(cell.inputs["B"][0] as lw::Int);
|
|
|
|
let output_state_id = cell.outputs["Y"][0] as lw::Int;
|
|
|
|
|
|
|
|
let output_a = lw::Output::new(output_state_id);
|
|
|
|
let output_a = lw::Output::new(output_state_id);
|
|
|
|
let output_b = lw::Output::new(output_state_id);
|
|
|
|
let output_b = lw::Output::new(output_state_id);
|
|
|
|
let peg = lw::Input::new(output_state_id);
|
|
|
|
let peg = lw::Input::new(output_state_id);
|
|
|
|
|
|
|
|
|
|
|
|
let buffer_a = lw::Component {
|
|
|
|
let buffer_a = lw::Component {
|
|
|
|
address: *next_address,
|
|
|
|
address: *next_address,
|
|
|
|
parent: parent_address,
|
|
|
|
parent: parent_address,
|
|
|
|
numeric_id: COMPONENT_MAP["MHG.Buffer_WithOutput"],
|
|
|
|
numeric_id: COMPONENT_MAP["MHG.Buffer_WithOutput"],
|
|
|
|
position: *next_position,
|
|
|
|
position: vec3_add(*next_position, [0, (i_bit as lw::Int) * 2 * SQUARE, 0]),
|
|
|
|
rotation: quaternion::id(),
|
|
|
|
rotation: quaternion::id(),
|
|
|
|
inputs: vec![input_a],
|
|
|
|
inputs: vec![input_a],
|
|
|
|
outputs: vec![output_a],
|
|
|
|
outputs: vec![output_a],
|
|
|
|
@ -391,7 +396,7 @@ fn or_gate(
|
|
|
|
address: *next_address + 1,
|
|
|
|
address: *next_address + 1,
|
|
|
|
parent: parent_address,
|
|
|
|
parent: parent_address,
|
|
|
|
numeric_id: COMPONENT_MAP["MHG.Buffer_WithOutput"],
|
|
|
|
numeric_id: COMPONENT_MAP["MHG.Buffer_WithOutput"],
|
|
|
|
position: vec3_add(*next_position, [SQUARE, 0, 0]),
|
|
|
|
position: vec3_add(*next_position, [SQUARE, (i_bit as lw::Int) * 2 * SQUARE, 0]),
|
|
|
|
rotation: quaternion::id(),
|
|
|
|
rotation: quaternion::id(),
|
|
|
|
inputs: vec![input_b],
|
|
|
|
inputs: vec![input_b],
|
|
|
|
outputs: vec![output_b],
|
|
|
|
outputs: vec![output_b],
|
|
|
|
@ -401,7 +406,10 @@ fn or_gate(
|
|
|
|
address: *next_address + 2,
|
|
|
|
address: *next_address + 2,
|
|
|
|
parent: parent_address,
|
|
|
|
parent: parent_address,
|
|
|
|
numeric_id: COMPONENT_MAP["MHG.Peg"],
|
|
|
|
numeric_id: COMPONENT_MAP["MHG.Peg"],
|
|
|
|
position: vec3_add(*next_position, [0, 0, 2 * SQUARE]),
|
|
|
|
position: vec3_add(
|
|
|
|
|
|
|
|
*next_position,
|
|
|
|
|
|
|
|
[0, (i_bit as lw::Int) * 2 * SQUARE, 2 * SQUARE],
|
|
|
|
|
|
|
|
),
|
|
|
|
rotation: quaternion::id(),
|
|
|
|
rotation: quaternion::id(),
|
|
|
|
inputs: vec![peg],
|
|
|
|
inputs: vec![peg],
|
|
|
|
outputs: vec![],
|
|
|
|
outputs: vec![],
|
|
|
|
@ -409,14 +417,29 @@ fn or_gate(
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
connection_map.insert(
|
|
|
|
connection_map.insert(
|
|
|
|
(cell.index, "A"),
|
|
|
|
Connection {
|
|
|
|
|
|
|
|
cell_index: cell.index,
|
|
|
|
|
|
|
|
port_name: "A",
|
|
|
|
|
|
|
|
bit_index: i_bit,
|
|
|
|
|
|
|
|
},
|
|
|
|
lw::PegAddress::input(buffer_a.address, 0),
|
|
|
|
lw::PegAddress::input(buffer_a.address, 0),
|
|
|
|
);
|
|
|
|
);
|
|
|
|
connection_map.insert(
|
|
|
|
connection_map.insert(
|
|
|
|
(cell.index, "B"),
|
|
|
|
Connection {
|
|
|
|
|
|
|
|
cell_index: cell.index,
|
|
|
|
|
|
|
|
port_name: "B",
|
|
|
|
|
|
|
|
bit_index: i_bit,
|
|
|
|
|
|
|
|
},
|
|
|
|
lw::PegAddress::input(buffer_b.address, 0),
|
|
|
|
lw::PegAddress::input(buffer_b.address, 0),
|
|
|
|
);
|
|
|
|
);
|
|
|
|
connection_map.insert((cell.index, "Y"), lw::PegAddress::input(peg.address, 0));
|
|
|
|
connection_map.insert(
|
|
|
|
|
|
|
|
Connection {
|
|
|
|
|
|
|
|
cell_index: cell.index,
|
|
|
|
|
|
|
|
port_name: "Y",
|
|
|
|
|
|
|
|
bit_index: i_bit,
|
|
|
|
|
|
|
|
},
|
|
|
|
|
|
|
|
lw::PegAddress::input(peg.address, 0),
|
|
|
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
|
|
wires.push(lw::Wire {
|
|
|
|
wires.push(lw::Wire {
|
|
|
|
first_point: lw::PegAddress::output(buffer_a.address, 0),
|
|
|
|
first_point: lw::PegAddress::output(buffer_a.address, 0),
|
|
|
|
@ -431,8 +454,98 @@ fn or_gate(
|
|
|
|
wire_rotation: 0.0,
|
|
|
|
wire_rotation: 0.0,
|
|
|
|
});
|
|
|
|
});
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
components.push(buffer_a);
|
|
|
|
|
|
|
|
components.push(buffer_b);
|
|
|
|
|
|
|
|
components.push(peg);
|
|
|
|
|
|
|
|
|
|
|
|
*next_address += 3;
|
|
|
|
*next_address += 3;
|
|
|
|
|
|
|
|
} else {
|
|
|
|
|
|
|
|
let component = lw::Component {
|
|
|
|
|
|
|
|
address: *next_address,
|
|
|
|
|
|
|
|
parent: parent_address,
|
|
|
|
|
|
|
|
numeric_id: COMPONENT_MAP[text_id],
|
|
|
|
|
|
|
|
position: vec3_add(*next_position, [0, (i_bit as lw::Int) * 2 * SQUARE, 0]),
|
|
|
|
|
|
|
|
rotation: quaternion::id(),
|
|
|
|
|
|
|
|
inputs: vec![input_a, input_b],
|
|
|
|
|
|
|
|
outputs: vec![output],
|
|
|
|
|
|
|
|
custom_data: vec![],
|
|
|
|
|
|
|
|
};
|
|
|
|
|
|
|
|
*next_address += 1;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
connection_map.insert(
|
|
|
|
|
|
|
|
Connection {
|
|
|
|
|
|
|
|
cell_index: cell.index,
|
|
|
|
|
|
|
|
port_name: "A",
|
|
|
|
|
|
|
|
bit_index: i_bit,
|
|
|
|
|
|
|
|
},
|
|
|
|
|
|
|
|
lw::PegAddress::input(component.address, 0),
|
|
|
|
|
|
|
|
);
|
|
|
|
|
|
|
|
connection_map.insert(
|
|
|
|
|
|
|
|
Connection {
|
|
|
|
|
|
|
|
cell_index: cell.index,
|
|
|
|
|
|
|
|
port_name: "B",
|
|
|
|
|
|
|
|
bit_index: i_bit,
|
|
|
|
|
|
|
|
},
|
|
|
|
|
|
|
|
lw::PegAddress::input(component.address, 1),
|
|
|
|
|
|
|
|
);
|
|
|
|
|
|
|
|
connection_map.insert(
|
|
|
|
|
|
|
|
Connection {
|
|
|
|
|
|
|
|
cell_index: cell.index,
|
|
|
|
|
|
|
|
port_name: "Y",
|
|
|
|
|
|
|
|
bit_index: i_bit,
|
|
|
|
|
|
|
|
},
|
|
|
|
|
|
|
|
lw::PegAddress::output(component.address, 0),
|
|
|
|
|
|
|
|
);
|
|
|
|
|
|
|
|
components.push(component);
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
next_position[2] += 5 * SQUARE;
|
|
|
|
next_position[2] += 5 * SQUARE;
|
|
|
|
|
|
|
|
|
|
|
|
return vec![buffer_a, buffer_b, peg];
|
|
|
|
return components;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fn unary_op(
|
|
|
|
|
|
|
|
cell: &Cell,
|
|
|
|
|
|
|
|
text_id: &str,
|
|
|
|
|
|
|
|
parent_address: u32,
|
|
|
|
|
|
|
|
next_address: &mut u32,
|
|
|
|
|
|
|
|
next_position: &mut Vector3<i32>,
|
|
|
|
|
|
|
|
wires: &mut Vec<lw::Wire>,
|
|
|
|
|
|
|
|
connection_map: &mut ConnectionMap,
|
|
|
|
|
|
|
|
) -> Vec<lw::Component> {
|
|
|
|
|
|
|
|
let input = lw::Input::new(cell.inputs["A"][0] as i32);
|
|
|
|
|
|
|
|
let output = lw::Output::new(cell.outputs["Y"][0] as i32);
|
|
|
|
|
|
|
|
let component = lw::Component {
|
|
|
|
|
|
|
|
address: *next_address,
|
|
|
|
|
|
|
|
parent: parent_address,
|
|
|
|
|
|
|
|
numeric_id: COMPONENT_MAP[text_id],
|
|
|
|
|
|
|
|
position: *next_position,
|
|
|
|
|
|
|
|
rotation: quaternion::id(),
|
|
|
|
|
|
|
|
inputs: vec![input],
|
|
|
|
|
|
|
|
outputs: vec![output],
|
|
|
|
|
|
|
|
custom_data: vec![],
|
|
|
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
connection_map.insert(
|
|
|
|
|
|
|
|
Connection {
|
|
|
|
|
|
|
|
cell_index: cell.index,
|
|
|
|
|
|
|
|
port_name: "A",
|
|
|
|
|
|
|
|
bit_index: 0,
|
|
|
|
|
|
|
|
},
|
|
|
|
|
|
|
|
lw::PegAddress::input(component.address, 0),
|
|
|
|
|
|
|
|
);
|
|
|
|
|
|
|
|
connection_map.insert(
|
|
|
|
|
|
|
|
Connection {
|
|
|
|
|
|
|
|
cell_index: cell.index,
|
|
|
|
|
|
|
|
port_name: "Y",
|
|
|
|
|
|
|
|
bit_index: 0,
|
|
|
|
|
|
|
|
},
|
|
|
|
|
|
|
|
lw::PegAddress::output(component.address, 0),
|
|
|
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
*next_address += 1;
|
|
|
|
|
|
|
|
next_position[2] += 3 * SQUARE;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
return vec![component];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
D4VID