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verilog2logicworld
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26 Commits (3d983f0b5d2335b7dcc1e88d1209342982beba85)
 

Author SHA1 Message Date
D4VID 3d983f0b5d Refactoring
3 weeks ago
D4VID df70909542 Remove todos
3 weeks ago
D4VID 86ecdca0e9 Remove debug map print
3 weeks ago
D4VID eca62daf30 Stack boards
3 weeks ago
D4VID aca55a7c2c Multi bit without boards
4 weeks ago
D4VID 18ef7c2914 Preparation for multi bit
4 weeks ago
D4VID 9ce03c7779 Add mount builder
4 weeks ago
D4VID 501881def1 Add exit codes
4 weeks ago
D4VID bcfe76cde0 Add command line arguments
4 weeks ago
D4VID 49504196aa Add inverter
4 weeks ago
D4VID 364839cd05 Use https for public submodule
1 month ago
D4VID d30d192cf6 Add README.md
1 month ago
D4VID 82b107f9d2 Improve inputs and outputs
1 month ago
D4VID 556725aaaf More outputs
1 month ago
D4VID 9763027d53 Connecting components
1 month ago
D4VID c6e261be73 Remove example
1 month ago
D4VID 6f173533db Placing basic components
1 month ago
D4VID 9c82d7c365 Remove debug json log
1 month ago
D4VID d532169d7c Use owned strings
1 month ago
D4VID 4649b1aad0 Label builder
1 month ago
D4VID dd5149930b Extracting cells from verilog modules
1 month ago
D4VID ea8370f33f Example subassembly
1 month ago
D4VID 5ae2c607d5 Add LICENCE
1 month ago
D4VID 84c3197fac Restructure project
1 month ago
D4VID 1579b5d82c Generating subassemblies
1 month ago
D4VID 9cadbd8990 Run yosys and get output
1 month ago