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verilog2logicworld
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Use layer builder for input and outputs

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master
D4VID 3 weeks ago
parent 858f752842
commit f56effc197
4 changed files with 171 additions and 124 deletions
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73
verilog2logicworld/src/cells/input_port.rs
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@ -0,0 +1,73 @@
use std::f32::consts::PI;
use logicworld_subassembly::{lw, COMPONENT_MAP};
use vecmath::{vec3_add, Vector3};
use crate::cells::builder;
use crate::router::{Connection, ConnectionMap, SQUARE};
pub fn input_port(
bits: &Vec<usize>,
port_name: &str,
parent_address: u32,
next_address: &mut u32,
next_position: &mut Vector3<lw::Int>,
connection_map: &mut ConnectionMap,
) -> Vec<lw::Component> {
let mut components = vec![];
let mut wires = vec![]; // discard
builder(
bits.len(),
parent_address,
next_address,
next_position,
&mut components,
&mut wires,
connection_map,
|i_bit, next_address, parent, next_position_within, components, _wires, connection_map| {
let bit_id = bits[i_bit];
let label = lw::Component {
address: *next_address,
parent,
numeric_id: COMPONENT_MAP["MHG.PanelLabel"],
position: *next_position_within,
rotation: quaternion::euler_angles(0.0, -PI / 2.0, 0.0),
inputs: vec![],
outputs: vec![],
custom_data: lw::Label::new(&format!("{}[{}]", port_name, i_bit))
.with_size(2.0)
.custom_data(),
};
*next_address += 1;
let peg = lw::Component {
address: *next_address,
parent,
numeric_id: COMPONENT_MAP["MHG.Peg"],
position: vec3_add(*next_position_within, [0, 0, SQUARE]),
rotation: quaternion::id(),
inputs: vec![lw::Input::new(bit_id as lw::Int)],
outputs: vec![],
custom_data: vec![],
};
connection_map.insert(
Connection {
cell_index: bit_id,
port_name: "input",
bit_index: 0,
},
lw::PegAddress::input(peg.address, 0),
);
components.push(label);
components.push(peg);
*next_address += 1;
},
);
next_position[0] += SQUARE / 3; // third of a square
return components;
}

8
verilog2logicworld/src/cells/mod.rs
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@ -2,7 +2,11 @@ mod builder;
use builder::builder;
pub mod unary_op;
pub use unary_op::unary_op;
pub mod binary_op;
pub mod input_port;
pub mod output_port;
pub use unary_op::unary_op;
pub use binary_op::binary_op;
pub use output_port::output_port;
pub use input_port::input_port;

73
verilog2logicworld/src/cells/output_port.rs
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@ -0,0 +1,73 @@
use std::f32::consts::PI;
use logicworld_subassembly::{lw, COMPONENT_MAP};
use vecmath::{vec3_add, Vector3};
use crate::cells::builder;
use crate::router::{Connection, ConnectionMap, SQUARE};
pub fn output_port(
bits: &Vec<usize>,
port_name: &str,
parent_address: u32,
next_address: &mut u32,
next_position: &mut Vector3<lw::Int>,
connection_map: &mut ConnectionMap,
) -> Vec<lw::Component> {
let mut components = vec![];
let mut wires = vec![]; // discard
builder(
bits.len(),
parent_address,
next_address,
next_position,
&mut components,
&mut wires,
connection_map,
|i_bit, next_address, parent, next_position_within, components, _wires, connection_map| {
let bit_id = bits[i_bit];
let label = lw::Component {
address: *next_address,
parent,
numeric_id: COMPONENT_MAP["MHG.PanelLabel"],
position: vec3_add(*next_position_within, [0, 0, SQUARE]),
rotation: quaternion::euler_angles(0.0, -PI / 2.0, 0.0),
inputs: vec![],
outputs: vec![],
custom_data: lw::Label::new(&format!("{}[{}]", port_name, i_bit))
.with_size(2.0)
.custom_data(),
};
*next_address += 1;
let peg = lw::Component {
address: *next_address,
parent,
numeric_id: COMPONENT_MAP["MHG.Peg"],
position: *next_position_within,
rotation: quaternion::id(),
inputs: vec![lw::Input::new(bit_id as lw::Int)],
outputs: vec![],
custom_data: vec![],
};
connection_map.insert(
Connection {
cell_index: bit_id,
port_name: "output",
bit_index: 0,
},
lw::PegAddress::input(peg.address, 0),
);
components.push(label);
components.push(peg);
*next_address += 1;
},
);
next_position[0] += SQUARE / 3; // third of a square
return components;
}

141
verilog2logicworld/src/router.rs
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@ -1,7 +1,7 @@
use std::{collections::HashMap, f32::consts::PI, fmt::Debug};
use logicworld_subassembly::{lw, COMPONENT_MAP};
use vecmath::{vec3_add, Vector3};
use vecmath::vec3_add;
use crate::verilog::{Error, Module};
use crate::cells::*;
@ -107,20 +107,15 @@ pub fn route(module: Module) -> Result<(Vec<lw::Component>, Vec<lw::Wire>), Erro
let mut next_input_position = origin.clone();
for input in &module.inputs {
for bit in &input.bits {
input_ports.extend(input_port(
*bit,
&input.name,
board_address,
&mut next_address,
&mut next_input_position,
&mut connection_map,
));
}
// align back to middle
next_input_position[0] += SQUARE / 2;
next_input_position[0] -= next_input_position[0] % SQUARE;
next_input_position[0] += SQUARE / 2;
input_ports.extend(input_port(
&input.bits,
&input.name,
board_address,
&mut next_address,
&mut next_input_position,
&mut connection_map,
));
next_input_position[0] += 3 * SQUARE;
}
let mut next_position = vec3_add(origin, [1 * SQUARE, 0, 3 * SQUARE]);
@ -171,20 +166,15 @@ pub fn route(module: Module) -> Result<(Vec<lw::Component>, Vec<lw::Wire>), Erro
let mut next_output_position = next_position.clone();
for output in &module.outputs {
for bit in &output.bits {
output_ports.extend(output_port(
*bit,
&output.name,
board_address,
&mut next_address,
&mut next_output_position,
&mut connection_map,
));
}
// align back to middle
next_output_position[0] += SQUARE / 2;
next_output_position[0] -= next_output_position[0] % SQUARE;
next_output_position[0] += SQUARE / 2;
output_ports.extend(output_port(
&output.bits,
&output.name,
board_address,
&mut next_address,
&mut next_output_position,
&mut connection_map,
));
next_output_position[0] += 3 * SQUARE;
}
let board = lw::Component {
@ -245,96 +235,3 @@ pub fn route(module: Module) -> Result<(Vec<lw::Component>, Vec<lw::Wire>), Erro
return Ok((components, wires));
}
fn input_port(
bit_id: usize,
port_name: &str,
parent_address: u32,
next_address: &mut u32,
next_position: &mut Vector3<lw::Int>,
connection_map: &mut ConnectionMap,
) -> Vec<lw::Component> {
let label = lw::Component {
address: *next_address,
parent: parent_address,
numeric_id: COMPONENT_MAP["MHG.PanelLabel"],
position: *next_position,
rotation: quaternion::euler_angles(0.0, -PI / 2.0, 0.0),
inputs: vec![],
outputs: vec![],
custom_data: lw::Label::new(port_name).with_size(2.0).custom_data(),
};
*next_address += 1;
let peg = lw::Component {
address: *next_address,
parent: parent_address,
numeric_id: COMPONENT_MAP["MHG.Peg"],
position: vec3_add(*next_position, [0, 0, SQUARE]),
rotation: quaternion::id(),
inputs: vec![lw::Input::new(bit_id as lw::Int)],
outputs: vec![],
custom_data: vec![],
};
connection_map.insert(
Connection {
cell_index: bit_id,
port_name: "input",
bit_index: 0,
},
lw::PegAddress::input(peg.address, 0),
);
*next_address += 1;
next_position[0] += SQUARE / 3; // third of a square
return vec![peg, label];
}
fn output_port(
bit_id: usize,
port_name: &str,
parent_address: u32,
next_address: &mut u32,
next_position: &mut Vector3<lw::Int>,
connection_map: &mut ConnectionMap,
) -> Vec<lw::Component> {
let label = lw::Component {
address: *next_address,
parent: parent_address,
numeric_id: COMPONENT_MAP["MHG.PanelLabel"],
position: vec3_add(*next_position, [0, 0, SQUARE]),
rotation: quaternion::euler_angles(0.0, -PI / 2.0, 0.0),
inputs: vec![],
outputs: vec![],
custom_data: lw::Label::new(port_name).with_size(2.0).custom_data(),
};
*next_address += 1;
let peg = lw::Component {
address: *next_address,
parent: parent_address,
numeric_id: COMPONENT_MAP["MHG.Peg"],
position: *next_position,
rotation: quaternion::id(),
inputs: vec![lw::Input::new(bit_id as lw::Int)],
outputs: vec![],
custom_data: vec![],
};
connection_map.insert(
Connection {
cell_index: bit_id,
port_name: "output",
bit_index: 0,
},
lw::PegAddress::input(peg.address, 0),
);
*next_address += 1;
next_position[0] += SQUARE / 3; // third of a square
return vec![peg, label];
}

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