Example subassembly

logicworld-subassembly

@@ -1 +1 @@
-Subproject commit 3ff75d8d16e7e676160da21889cce2992ee912b3
+Subproject commit 373860674228f199c57344be19a4e32c759371e9

verilog2logicworld/src/main.rs

@@ -5,6 +5,7 @@ use std::path::Path;
 
 use logicworld_subassembly::create_subassembly;
 use logicworld_subassembly::lw;
+use logicworld_subassembly::lw::PegAddress;
 use logicworld_subassembly::COMPONENT_MAP;
 use verilog::run_yosys;
 
@@ -20,21 +21,36 @@ fn write_subassembly() -> io::Result<()> {
             outputs: vec![],
             custom_data: lw::CircuitBoard::default()
                 .with_color(0, 100, 50)
-                .with_size(10, 10)
+                .with_size(5, 10)
                 .custom_data(),
         },
         lw::Component {
             address: 2,
             parent: 1,
             numeric_id: COMPONENT_MAP["MHG.AndGate"],
-            position: [800, 150, 750],
+            position: [150+1*300, 150, 150+2*300],
-            rotation: (0.1, [0.2, 0.4, 0.5]),
+            rotation: quaternion::id(),
             inputs: vec![lw::Input::new(1), lw::Input::new(2), lw::Input::new(3)],
             outputs: vec![lw::Output::new(4)],
             custom_data: vec![],
         },
+        lw::Component {
+            address: 3,
+            parent: 1,
+            numeric_id: COMPONENT_MAP["MHG.XorGate"],
+            position: [150+1*300, 150, 150+5*300],
+            rotation: quaternion::id(),
+            inputs: vec![lw::Input::new(5), lw::Input::new(4)],
+            outputs: vec![lw::Output::new(6)],
+            custom_data: vec![],
+        },
     ];
-    let wires = vec![];
+    let wires = vec![lw::Wire {
+        first_point: PegAddress::output(2, 0),
+        second_point: PegAddress::input(3, 1),
+        circuit_state_id: 4,
+        wire_rotation: 0.0,
+    }];
 
     create_subassembly(
         "test".to_owned(),