More outputs

verilog2logicworld/gates.v

@@ -1,3 +1,7 @@
-module gates(input a, input b, input c, output wire out);
+module gates(
+    input a,b,c,d,
+    output wire out, out2
+);
     assign out = a & b | c;
+    assign out2 = a & b ^ d;
 endmodule