Test memory loads

master
D4VID 8 months ago
parent b6c2070353
commit 40f55064ce

@ -1,10 +1,7 @@
#![no_std]
#![no_main]
use core::{
panic::PanicInfo,
ptr::{read_volatile, write_volatile},
};
use core::{panic::PanicInfo, ptr::{read_volatile, write_volatile}};
use riscv_rt::entry;
#[panic_handler]
@ -17,23 +14,19 @@ static TEXT: &str = "lmao YEET";
#[entry]
fn main() -> ! {
const MEM_ADDR: *mut u32 = 0x8000_0004 as *mut u32;
const MEM_ADDR_2: *mut i32 = 0x8000_0008 as *mut i32;
loop {
unsafe {
write_volatile(MEM_ADDR, 0b11011011);
for _ in 0..32 {
let mut value = read_volatile(MEM_ADDR);
value <<= 1;
write_volatile(MEM_ADDR, value);
}
write_volatile(0x8000_0000 as *mut u32, 0x03020100);
write_volatile(MEM_ADDR_2, -0x50000000);
for _ in 0..32 {
let mut value = read_volatile(MEM_ADDR_2);
value >>= 1;
write_volatile(MEM_ADDR_2, value);
}
let _ = read_volatile(0x8000_0000 as *mut u32);
let _ = read_volatile(0x8000_0000 as *mut u16);
let _ = read_volatile(0x8000_0002 as *mut u16);
let _ = read_volatile(0x8000_0000 as *mut u8);
let _ = read_volatile(0x8000_0001 as *mut u8);
let _ = read_volatile(0x8000_0002 as *mut u8);
let _ = read_volatile(0x8000_0003 as *mut u8);
}
}
}

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