From c6e261be732fb5d659b3e370a25c777aa91770d6 Mon Sep 17 00:00:00 2001
From: D4VID <d4vid@d4vid.xyz>
Date: Tue, 19 Aug 2025 17:16:20 +0200
Subject: [PATCH] Remove example

---
 verilog2logicworld/src/main.rs | 73 ----------------------------------
 1 file changed, 73 deletions(-)

diff --git a/verilog2logicworld/src/main.rs b/verilog2logicworld/src/main.rs
index 32be719..8c3bee7 100644
--- a/verilog2logicworld/src/main.rs
+++ b/verilog2logicworld/src/main.rs
@@ -1,85 +1,12 @@
 mod router;
 mod verilog;
 
-use std::f32::consts::PI;
-use std::io;
 use std::path::Path;
 
 use logicworld_subassembly::create_subassembly;
-use logicworld_subassembly::lw;
-use logicworld_subassembly::COMPONENT_MAP;
 use verilog::compile_module;
 use verilog::get_modules;
 
-fn write_subassembly() -> io::Result<()> {
-    let components = vec![
-        lw::Component {
-            address: 1,
-            parent: 0,
-            numeric_id: COMPONENT_MAP["MHG.CircuitBoard"],
-            position: [0, 0, 0],
-            rotation: quaternion::id(),
-            inputs: vec![],
-            outputs: vec![],
-            custom_data: lw::CircuitBoard::default()
-                .with_color(0, 100, 50)
-                .with_size(5, 13)
-                .custom_data(),
-        },
-        lw::Component {
-            address: 2,
-            parent: 1,
-            numeric_id: COMPONENT_MAP["MHG.AndGate"],
-            position: [150 + 1 * 300, 150, 150 + 7 * 300],
-            rotation: quaternion::id(),
-            inputs: vec![lw::Input::new(1), lw::Input::new(2), lw::Input::new(3)],
-            outputs: vec![lw::Output::new(4)],
-            custom_data: vec![],
-        },
-        lw::Component {
-            address: 3,
-            parent: 1,
-            numeric_id: COMPONENT_MAP["MHG.XorGate"],
-            position: [150 + 1 * 300, 150, 150 + 10 * 300],
-            rotation: quaternion::id(),
-            inputs: vec![lw::Input::new(5), lw::Input::new(4)],
-            outputs: vec![lw::Output::new(6)],
-            custom_data: vec![],
-        },
-        lw::Component {
-            address: 4,
-            parent: 1,
-            numeric_id: COMPONENT_MAP["MHG.PanelLabel"],
-            position: [150 + 3 * 300, 150, 150 + 1 * 300],
-            rotation: quaternion::euler_angles(0.0, -PI / 2.0, 0.0),
-            inputs: vec![],
-            outputs: vec![],
-            custom_data: lw::Label::new("Lmao")
-                .mono()
-                .with_size(2.5)
-                .with_color(0, 100, 250)
-                .with_align(lw::HorizontalAlign::Right, lw::VerticalAlign::Bottom)
-                .with_dimensions(4, 3)
-                .custom_data(),
-        },
-    ];
-    let wires = vec![lw::Wire {
-        first_point: lw::PegAddress::output(2, 0),
-        second_point: lw::PegAddress::input(3, 1),
-        circuit_state_id: 4,
-        wire_rotation: 0.0,
-    }];
-
-    create_subassembly(
-        "test".to_owned(),
-        &Path::new("output/"),
-        &components,
-        &wires,
-    )?;
-
-    return Ok(());
-}
-
 fn main() {
     let files = ["gates.v"];
     let result = get_modules(&files);