diff --git a/verilog2logicworld/src/cells/binary_op.rs b/verilog2logicworld/src/cells/binary_op.rs
index 55c0cb5..6ddf99b 100644
--- a/verilog2logicworld/src/cells/binary_op.rs
+++ b/verilog2logicworld/src/cells/binary_op.rs
@@ -179,7 +179,7 @@ pub fn binary_op(
         },
     );
 
-    next_position[2] += 5 * SQUARE;
+    next_position[2] += 4 * SQUARE;
 
     return components;
 }