From 49504196aa837463297d29aff36bd73cefd488b3 Mon Sep 17 00:00:00 2001
From: D4VID <d4vid@d4vid.xyz>
Date: Wed, 20 Aug 2025 08:53:22 +0200
Subject: [PATCH] Add inverter

---
 verilog2logicworld/src/router.rs | 50 ++++++++++++++++++++++++++++++--
 1 file changed, 47 insertions(+), 3 deletions(-)

diff --git a/verilog2logicworld/src/router.rs b/verilog2logicworld/src/router.rs
index 04082cd..f16f887 100644
--- a/verilog2logicworld/src/router.rs
+++ b/verilog2logicworld/src/router.rs
@@ -99,7 +99,7 @@ pub fn route(module: Module) -> Result<(Vec<lw::Component>, Vec<lw::Wire>), Erro
     for (i, cell) in module.cells.iter().enumerate() {
         println!("{}: {:?}", i, cell);
         let components = match cell.cell_type.as_str() {
-            "$and" => basic_gate(
+            "$and" => binary_op(
                 cell,
                 "MHG.AndGate",
                 board_address,
@@ -107,7 +107,7 @@ pub fn route(module: Module) -> Result<(Vec<lw::Component>, Vec<lw::Wire>), Erro
                 &mut next_position,
                 &mut connection_map,
             ),
-            "$xor" => basic_gate(
+            "$xor" => binary_op(
                 cell,
                 "MHG.XorGate",
                 board_address,
@@ -123,6 +123,14 @@ pub fn route(module: Module) -> Result<(Vec<lw::Component>, Vec<lw::Wire>), Erro
                 &mut wires,
                 &mut connection_map,
             ),
+            "$not" => unary_op(
+                cell,
+                "MHG.Inverter",
+                board_address,
+                &mut next_address,
+                &mut next_position,
+                &mut connection_map,
+            ),
             _ => return Err(Error::UnsupportedCell),
         };
         cells.extend(components);
@@ -277,7 +285,7 @@ fn output_port(
     return vec![peg, label];
 }
 
-fn basic_gate(
+fn binary_op(
     cell: &Cell,
     text_id: &str,
     parent_address: u32,
@@ -318,6 +326,42 @@ fn basic_gate(
     return vec![component];
 }
 
+fn unary_op(
+    cell: &Cell,
+    text_id: &str,
+    parent_address: u32,
+    next_address: &mut u32,
+    next_position: &mut Vector3<i32>,
+    connection_map: &mut HashMap<(usize, &str), lw::PegAddress>,
+) -> Vec<lw::Component> {
+    let input = lw::Input::new(cell.inputs["A"][0] as i32);
+    let output = lw::Output::new(cell.outputs["Y"][0] as i32);
+    let component = lw::Component {
+        address: *next_address,
+        parent: parent_address,
+        numeric_id: COMPONENT_MAP[text_id],
+        position: *next_position,
+        rotation: quaternion::id(),
+        inputs: vec![input],
+        outputs: vec![output],
+        custom_data: vec![],
+    };
+
+    connection_map.insert(
+        (cell.index, "A"),
+        lw::PegAddress::input(component.address, 0),
+    );
+    connection_map.insert(
+        (cell.index, "Y"),
+        lw::PegAddress::output(component.address, 0),
+    );
+
+    *next_address += 1;
+    next_position[2] += 3 * SQUARE;
+
+    return vec![component];
+}
+
 fn or_gate(
     cell: &Cell,
     parent_address: u32,