From 4649b1aad0ed2e423b2553524588675f2d40fe02 Mon Sep 17 00:00:00 2001
From: D4VID <d4vid@d4vid.xyz>
Date: Tue, 19 Aug 2025 11:40:13 +0200
Subject: [PATCH] Label builder

---
 logicworld-subassembly         |  2 +-
 verilog2logicworld/src/main.rs | 32 ++++++++++++++++++++++++--------
 2 files changed, 25 insertions(+), 9 deletions(-)

diff --git a/logicworld-subassembly b/logicworld-subassembly
index 3738606..9801e5d 160000
--- a/logicworld-subassembly
+++ b/logicworld-subassembly
@@ -1 +1 @@
-Subproject commit 373860674228f199c57344be19a4e32c759371e9
+Subproject commit 9801e5d6c87db31a616de50195110266ed00c15c
diff --git a/verilog2logicworld/src/main.rs b/verilog2logicworld/src/main.rs
index 326680c..d56fe5b 100644
--- a/verilog2logicworld/src/main.rs
+++ b/verilog2logicworld/src/main.rs
@@ -1,11 +1,11 @@
 mod verilog;
 
+use std::f32::consts::PI;
 use std::io;
 use std::path::Path;
 
 use logicworld_subassembly::create_subassembly;
 use logicworld_subassembly::lw;
-use logicworld_subassembly::lw::PegAddress;
 use logicworld_subassembly::COMPONENT_MAP;
 use verilog::compile_module;
 use verilog::get_modules;
@@ -22,14 +22,14 @@ fn write_subassembly() -> io::Result<()> {
             outputs: vec![],
             custom_data: lw::CircuitBoard::default()
                 .with_color(0, 100, 50)
-                .with_size(5, 10)
+                .with_size(5, 13)
                 .custom_data(),
         },
         lw::Component {
             address: 2,
             parent: 1,
             numeric_id: COMPONENT_MAP["MHG.AndGate"],
-            position: [150+1*300, 150, 150+2*300],
+            position: [150 + 1 * 300, 150, 150 + 7 * 300],
             rotation: quaternion::id(),
             inputs: vec![lw::Input::new(1), lw::Input::new(2), lw::Input::new(3)],
             outputs: vec![lw::Output::new(4)],
@@ -39,16 +39,32 @@ fn write_subassembly() -> io::Result<()> {
             address: 3,
             parent: 1,
             numeric_id: COMPONENT_MAP["MHG.XorGate"],
-            position: [150+1*300, 150, 150+5*300],
+            position: [150 + 1 * 300, 150, 150 + 10 * 300],
             rotation: quaternion::id(),
             inputs: vec![lw::Input::new(5), lw::Input::new(4)],
             outputs: vec![lw::Output::new(6)],
             custom_data: vec![],
         },
+        lw::Component {
+            address: 4,
+            parent: 1,
+            numeric_id: COMPONENT_MAP["MHG.PanelLabel"],
+            position: [150 + 3 * 300, 150, 150 + 1 * 300],
+            rotation: quaternion::euler_angles(0.0, -PI / 2.0, 0.0),
+            inputs: vec![],
+            outputs: vec![],
+            custom_data: lw::Label::new("Lmao")
+                .mono()
+                .with_size(2.5)
+                .with_color(0, 100, 250)
+                .with_align(lw::HorizontalAlign::Right, lw::VerticalAlign::Bottom)
+                .with_dimensions(4, 3)
+                .custom_data(),
+        },
     ];
     let wires = vec![lw::Wire {
-        first_point: PegAddress::output(2, 0),
-        second_point: PegAddress::input(3, 1),
+        first_point: lw::PegAddress::output(2, 0),
+        second_point: lw::PegAddress::input(3, 1),
         circuit_state_id: 4,
         wire_rotation: 0.0,
     }];
@@ -78,6 +94,6 @@ fn main() {
         println!("{}: {:?}", module, result);
     }
 
-    // let result = write_subassembly();
-    // println!("{:?}", result);
+    let result = write_subassembly();
+    println!("{:?}", result);
 }