From d19d7cd94c764c73e5ab983baed5e6e4ddb1ee80 Mon Sep 17 00:00:00 2001 From: D4VID Date: Mon, 18 Aug 2025 18:25:53 +0200 Subject: [PATCH] Add constructors for inputs and outputs --- logicworld-subassembly/src/lib.rs | 27 ++++++++++++++++++++++----- logicworld-subassembly/src/lw.rs | 10 ++++++++++ 2 files changed, 32 insertions(+), 5 deletions(-) diff --git a/logicworld-subassembly/src/lib.rs b/logicworld-subassembly/src/lib.rs index d2e9e70..eb57693 100644 --- a/logicworld-subassembly/src/lib.rs +++ b/logicworld-subassembly/src/lib.rs @@ -1,11 +1,22 @@ use std::{ - fs::{self, File}, i32, io::{self, Write}, path::Path + fs::{self, File}, + io::{self, Write}, + path::Path, }; use crate::lw::{BinarySerializable, ComponentIdMap, ModVersion, Version}; pub mod lw; +// Convert component text id into numeric id +pub fn component_id(text_id: &str) -> i16 { + match text_id { + "MHG.CircuitBoard" => 1, + "MHG.AndGate" => 2, + _ => -1, + } +} + enum SaveType { _World = 1, Subassembly = 2, @@ -56,10 +67,16 @@ fn write_subassembly_file( }]; mods.write_to(file)?; - let component_id_map = vec![ComponentIdMap { - numeric_id: 15, - text_id: "MHG.CircuitBoard".to_owned(), - }]; + let component_id_map = vec![ + ComponentIdMap { + numeric_id: 1, + text_id: "MHG.CircuitBoard".to_owned(), + }, + ComponentIdMap { + numeric_id: 2, + text_id: "MHG.AndGate".to_owned(), + }, + ]; component_id_map.write_to(file)?; for component in components { diff --git a/logicworld-subassembly/src/lw.rs b/logicworld-subassembly/src/lw.rs index 0883c43..ad4363a 100644 --- a/logicworld-subassembly/src/lw.rs +++ b/logicworld-subassembly/src/lw.rs @@ -47,10 +47,20 @@ pub struct ModVersion { pub struct Input { circuit_state_id: Int, } +impl Input { + pub fn new(circuit_state_id: Int) -> Self { + Self { circuit_state_id } + } +} #[derive(BinarySerializable)] pub struct Output { circuit_state_id: Int, } +impl Output { + pub fn new(circuit_state_id: Int) -> Self { + Self { circuit_state_id } + } +} #[derive(BinarySerializable)] pub struct ComponentIdMap {