From 2617424501cef3ec9f43cf58c9e1ae39d459d81b Mon Sep 17 00:00:00 2001 From: D4VID Date: Mon, 18 Aug 2025 18:04:29 +0200 Subject: [PATCH] Add a builder for circuit board custom data --- logicworld-subassembly/src/lw.rs | 35 ++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/logicworld-subassembly/src/lw.rs b/logicworld-subassembly/src/lw.rs index 10d9cde..0883c43 100644 --- a/logicworld-subassembly/src/lw.rs +++ b/logicworld-subassembly/src/lw.rs @@ -85,6 +85,41 @@ pub struct Wire { wire_rotation: Float, } +pub struct CircuitBoard { + color: Vec, + width: Int, + height: Int, +} +impl Default for CircuitBoard { + fn default() -> Self { + Self { + color: vec![51, 51, 51], + width: 1, + height: 1, + } + } +} +impl CircuitBoard { + pub fn with_color(&mut self, r: u8, g: u8, b: u8) -> &mut Self { + self.color[0] = r; + self.color[1] = g; + self.color[2] = b; + return self; + } + pub fn with_size(&mut self, width: Int, height: Int) -> &mut Self { + self.width = width; + self.height = height; + return self; + } + pub fn custom_data(&self) -> Vec { + let mut custom_data = Vec::with_capacity(11); + custom_data.extend(&self.color); + custom_data.extend(&self.width.to_le_bytes()); + custom_data.extend(&self.height.to_le_bytes()); + return custom_data; + } +} + impl BinarySerializable for Vec { fn write_to(&self, writer: &mut W) -> io::Result<()> { writer.write_all(&(self.len() as Int).to_le_bytes())?;